DAC 2026 Recap & DVCon India 2026 Preview: Agentic AI, RISC-V & The EDA Frontier

Is agentic AI genuinely transforming chip design, or is it merely accelerating decades-old workflows? In this episode of EEHerald Silicon Bridge, hosts Poojitha, Kubra, Ashish Rao, and Srinivas Reddy recap the biggest takeaways from DAC 2026 and preview what to expect at DVCon India 2026 in Bengaluru.

Episode Highlights:

• DAC 2026 & AI Realities: How agentic AI tools moved from investor slide decks to floor production, featuring real metrics from Bronco AI, ChipAgents, and Verkor.io, alongside the debate around "Davidmann's Test."
• Grassroots Silicon & Open-Source EDA: MeitY’s C2S program driving 255 tape-outs across 70 academic institutions, plus commercializing open-source EDA and the rise of homegrown RISC-V SoCs.
• DVCon India 2026 Preview (Sept 1–3): A breakdown of key sessions in Bengaluru, including static sign-off, agentic RTL verification, zero-fusing security, and the startup resurgence panel.
• The AI Debate — Proof vs. Prompt: Keynotes to watch, featuring Synopsys on GenAI's viability and Axiomise on why AI silicon requires formal verification proof over prompts.
• Physical Systems, Chiplets & RISC-V: Dedicated tracks covering UCIe chiplet verification, LPDDR6, formal tensor pipelines, and shifting workforce dynamics into the 2030s.